Technical Field
The present invention relates to a data writing method, and more particularly, to a data writing method for a rewritable non-volatile memory module, a memory control circuit unit and a memory storage apparatus using the same.
Description of Related Art
The growth of digital cameras, mobile phones, and MP3 players has been rapid in recent years. Consequently, the consumers' demand for storage media has increased tremendously. A rewritable non-volatile memory is one of the most adaptable memories for portable electronic products such as laptop computer due to its data non-volatility, low power consumption, small volume, non-mechanical structure and high read/write speed. A solid state drive (SSD) is a memory storage apparatus which utilizes a flash memory as its storage medium. For these reasons, the flash memory has become an import part of the electronic industries.
Based on memorable bits of each memory cell, a NAND-type flash memory may be classified into a Single Level Cell (SLC) NAND-type flash memory, a Multi Level Cell (MLC) NAND-type flash memory and a Trinary Level Cell (TLC) NAND-type flash memory. Therein, each memory cell of the SLC NAND-type flash memory is capable of storing one bit data (i.e., “1” and “0”), each memory cell of the MLC NAND-type flash memory is capable of storing two bits data, and each memory cell of the TLC NAND-type flash memory is capable of storing three bits data.
In the NAND-type flash memory, physical programming units are constituted by a plurality of memory cells arranged in the same word line. Because each memory cell of the SLC NAND-type flash memory is capable of storing one bit of data, the memory cells arranged on the same word line are corresponding to one physical programming unit in the SLC NAND-type flash memory.
In comparison with the SLC NAND-type flash memory, a floating gate storage layer of each memory cell of the MLC NAND-type flash memory is capable of storing two bits data. Therein, each storage state (i.e., “11”, “10”, “01” and “00”) includes a LSB (Least Significant Bit) and a MSB (Most Significant Bit). For instance, in the storage state, a value of a first bit counted from the left is the LSB, and a value of a second bit counted from the left is the MSB. Accordingly, the memory cells arranged on the same word line can constitute two physical programming units. Herein, the physical programming units constituted by the LSBs of said memory cells are known as a lower physical programming unit, and the physical programming units constituted by the MSBs of said memory cells are known as an upper physical programming unit. Particularly, a writing speed of the lower physical programming unit is faster than a writing speed of the upper physical programming unit, and data stored in the lower physical programming unit may be lost due to errors occurred while programming the upper physical programming unit.
Similarly, each memory cell in the TLC NAND-type flash memory is capable of storing three bits data, wherein each storage state (i.e., “111”, “110”, “101”, “100”, “011”, “010”, “001” and “000”) includes a first bit counted from the left being the LSB, a second bit counted from the left being a CSB (Center Significant Bit) and a third bit counted from the left being the MSB. Accordingly, the memory cells arranged on the same word line can constitute three physical programming units. Herein, the physical programming units constituted by the LSBs of said memory cells are known as the lower physical programming unit, the physical programming units constituted by the CSBs of said memory cells are known as a center physical programming unit, and the physical programming units constituted by the MSBs of said memory cells are known as the upper physical programming unit. Particularly, while programming memory cells arranged on the same word line, the stored data may be lost unless only the lower physical programming unit is programmed or all of the lower physical programming unit, the center physical programming unit and the upper physical programming unit are simultaneously programmed.
Generally, in order to prolong an operating life time of the TLC NAND-type flash memory module, a part of physical erasing units therein is programmed in a single-page mode (which only operates in the lower physical programming unit) for simulating operations of the SLC NAND-type flash memory. By doing so, the speed for writing and reading may also be improved since only the lower physical programming units are operated. The part of physical erasing units simulating the operation mode of the SLC NAND-type flash memory may be used to serve as a temporary area of the memory module, which is configured to temporarily store data or store system data. However, in comparison with the physical erasing units operated in the single-page mode, the operating life of the physical erasing units operated in the multi-page mode is relatively shorter, a threshold of a writing or erasing count of the physical erasing units operated in the multi-page mode is lower than a threshold of a writing or erasing count of the physical erasing units operated in the single-page mode, and the speed of the writing or erasing count of the physical erasing units operated in the multi-page mode is slower than the speed of the writing or erasing count of the physical erasing units operated in the single-page mode.
Based on the above, it is one of the major subjects in the industry as how to avoid rapid decline in the operating life of the physical erasing unit operated by using the multi-page mode while improving reliability and access speed of the flash memory having each memory cell capable of storing multiple bits.
Nothing herein may be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.